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Extra info for Emerging Nanotechnologies -Test Defect Tolerance and Reliability -SP
We simply shift all the arrows along the diagonals to obtain the three allocations. Similarly, for TG S and TG E, four allocations are needed. In Step 9, initially all nanoblocks and switchblocks are deemed to be defective. If a BUT produces the correct outputs for all the applied FDCs, it is deemed to be defect-free. A nanoblock cannot be recovered if any nanoblock or switchblock in the same TG is defective. However, we can use recovered nanoblocks and/or external circuits that are not adjacent to, but are reachable from the candidate defective block, as its TPG and ORA.
For a defect-free BUT, since each output port is connected to an inline NDR, the latches are driven to “1”. However, a line with a stuck-at-0 and/or stuck-open fault will fail to drive its associated NDR to the “1” state. By using a k-input AND gate as an ORA, any stuck-at-0 and stuck-open fault on a line can be detected. Category 1(a) includes two conﬁgurations, one corresponding to TG SE and the other corresponding to TG E. The TG, BUT and ORA for TG SE are shown in Fig. 8. Similarly, in Category 1(b) shown in Fig.
These thresholds become sharper as larger circuits are considered. Thus identifying the threshold locations gives useful guidelines for circuits feasible to implement with given defect rates and crossbar sizes. Chapter 1: Defect-Tolerant Logic with Nanoscale Crossbar Circuits 29 More generally, thresholds are seen in many properties of numerous combinatorial structures, such as random graphs , and related search algorithms . Of particular interest in our context are the thresholds in existence of various subgraphs  and extensions to any monotone property of graphs with various geometries [12,13].